The present invention relates generally to a clock cell for an integrated circuit, and, more particularly, to a gated clock gating cell.
Digital circuits use clock signals for synchronizing operations between different functional blocks. A functional block may refer to multiple storage elements including flip-flops and latches that generate an output based on the clock signals. However, the storage elements are not always required to alter their output states during operation and providing a continuous clock input signal at clock input terminals of the storage elements causes repetitive charging and discharging of the capacitive load associated with the clock input terminals, which can lead to high power consumption.
To reduce power consumption, clock input signals are switched using clock gating circuits or cells to obtain gated clock input signals. The gated clock input signals toggle only when logic states of the storage elements need to be changed.
FIG. 1 shows a schematic block diagram of a conventional clock gating cell 100. The conventional clock gating cell 100 includes a latch 102 that has an input terminal 104, a clock input terminal 106, an output terminal 108. An AND gate 110 is connected to the output terminal 108. An input signal (D) is provided at the input terminal 104 and a clock input signal (CLK) is provided at the clock input terminal 106. The clock input signal CLK toggles between logic high and low states. When the clock input signal CLK goes low, the latch 102 latches the input signal D, i.e., an output signal (Q) is generated at the output terminal 108. When the clock input signal CLK goes high, the output signal Q remains latched to in the previous state. The output signal Q and the clock input signal CLK are provided at input terminals of the AND gate 110, which generates a gated clock signal (GATE_CLK). Since the clock input signal CLK is gated using the output signal Q, the gated clock signal GATE_CLK toggles only when the state of the output signal Q changes. Thus, the gated clock signal GATE_CLK toggles only when an enable signal (provided as the input signal D) switches to a logic high.
However, the clock input signal CLK continues to toggle at the clock input terminal 106 of the latch 102 irrespective of changes in the output state of the latch 102, which leads to continuous charging and discharging of input capacitance at the clock input terminal 106, which increases the power dissipation and power consumption of the conventional clock gating cell 100.
Therefore, it would be advantageous to have a clock gating cell that reduces the toggling of the clock input signal CLK at the clock input terminal of the latch, that has low dynamic power dissipation and consumption, and that overcomes the above-mentioned limitations of conventional clock gating cells.